Electronic component package and manufacturing method thereof

ABSTRACT

An electronic component package and a manufacturing method thereof. The electronic component package includes: an insulation layer; a single layer of circuit pattern buried in the insulation layer and having a surface exposed at one side of the insulation layer, the circuit pattern comprising a bonding pad and a solder ball pad; and an electronic component mounted on one side of the insulation layer and electrically connected with the bonding pad. In addition, the electronic component package includes a portion of the insulation layer being removed in correspondence with the position of the solder ball pad such that the solder ball pad is exposed at the other side of the insulation layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a U.S. divisional application filed under 35 USC1.53(b) claiming priority benefit of U.S. Ser. No. 11/708,567 filed inthe United States on Feb. 21, 2007, which claims earlier prioritybenefit to Korean Patent Application No. 10-2006-0050015 filed with theKorean Intellectual Property Office on Jun. 2, 2006, the disclosures ofwhich are incorporated herein by reference.

BACKGROUND

1. Field

The present invention relates to an electronic component package and amanufacturing method thereof.

2. Description of the Related Art

With advances in the electronics industry, there is a rapid increase inthe use of electronic component packages, which are electronic devicesequipped with electronic components. Accordingly, there is an increasein the number of companies that manufacture and supply these electroniccomponent packages, as well as companies that are expanding theirbusiness with regards electronic component packages. These marketconditions have intensified competition in the pricing of electroniccomponent packages, whereby the prices of electronic component packagesare gradually decreasing, and there are several proposals being made forways to reduce costs.

At present, most electronic component packages are implemented, as inFIGS. 1 a and 1 b, by the method of connecting an electronic component(memory chip) using wire bonding to a substrate to provide a package,where this board is referred to as a BOC (Board-on-Chip). A BOC is aboard specially developed for the properties of the electroniccomponent, with the pad of the electronic component positioned in thecenter and with a structure allowing direct connection from the pad tothe board for increased signal processing speed. In order to attach theelectronic component at the bottom of the board and directly connect thepad to the board, a slot is formed in the portion where the pad ispositioned through which the wire bonding may be implemented. Thus, onlyone layer is needed for the metal layer of the board, which enables alow manufacturing cost and provides an advantage in the pricecompetitiveness of the electronic component package.

However, with the highly rapid development of semiconductormanufacturing technology, the capacity of the electronic componentpackage has also increased. Due to these developments in technology,there have been cases of signal loss at the wires when using aconventional BOC.

SUMMARY

An aspect of the present invention is to provide an electronic componentpackage and manufacturing method thereof, with which a high-capacityelectronic component can be installed on a single metal layer.

One aspect of the invention provides a method of manufacturing anelectronic component package, which includes: forming a protrusion parton a first carrier board; stacking an insulation layer on the firstcarrier board and forming a circuit pattern, which includes a bondingpad and a solder ball pad, on the surface of the insulation layer;mounting an electronic component on the surface of the insulation layerand electrically connecting the electronic component and the bondingpad; and removing the first carrier board and the protrusion part. Thiselectronic component package allows the mounting of the electroniccomponent with just a single circuit pattern layer.

The method may further include removing a portion of the insulationlayer to expose the solder ball pad, after the operation of removing thefirst carrier board and the protrusion part. The solder ball pad is theportion where a solder ball is to be attached, and thus it may beexposed to the exterior.

It may be advantageous for the operation of forming a protrusion part toinclude: stacking a seed layer on the first carrier board; stacking adry film on the seed layer; and removing a portion of the dry film toform the protrusion part.

Also, the operation of forming a protrusion part may include attachingtwo of the first carrier boards such that the first carrier boards faceopposite directions, and the operation of removing a portion of the dryfilm may include forming the protrusion part on each of the two firstcarrier boards. By using two first carrier boards, the efficiency of theprocess may be increased.

The operation of stacking an insulation layer and forming a circuitpattern may include: stacking a seed layer on a second carrier board;forming the circuit pattern on the seed layer; stacking the secondcarrier board on the insulation layer such that the circuit patternfaces the insulation layer; removing the second carrier board; andremoving the seed layer.

Also, the method may further include the operations of stacking a dryfilm on the seed layer and removing a portion of the dry film to exposethe seed layer on the side of the bonding pad; removing the seed layeraround the bonding pad; and surface-treating the bonding pad bysupplying a voltage to the remaining seed layer, between the operationof removing the second carrier board and the operation of removing theseed layer. This is a method of performing surface-treatment utilizingthe seed layer as a lead wire.

Another aspect of the invention provides an electronic componentpackage, which includes: an insulation layer; a single layer of circuitpattern buried in the insulation layer, which includes a bonding pad anda solder ball pad, and which has a surface exposed at one side of theinsulation layer; and an electronic component mounted on one side of theinsulation layer and electrically connected with the bonding pad. Inthis package, an electronic component is mounted with just a singlecircuit pattern layer.

Meanwhile, it may be desirable that a portion of the insulation layer beremoved in correspondence with the position of the solder ball pad, suchthat the solder ball pad is exposed at the other side of the insulationlayer. The solder ball pad becomes the point where a solder ball isattached.

Additional aspects and advantages of the invention will become apparentand more readily appreciated from the following description, includingthe appended drawings and claims, or may be learned by practice of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 a is a perspective view of an electronic component packageaccording to prior art.

FIG. 1 b is a cross-sectional view of an electronic component packageaccording to prior art.

FIG. 2 is a flowchart of a method of manufacturing an electroniccomponent package according to a first disclosed embodiment of theinvention.

FIG. 3 is a process diagram of a method of manufacturing an electroniccomponent package according to a first disclosed embodiment of theinvention.

FIG. 4 is a process diagram of a method of manufacturing an electroniccomponent package according to a second disclosed embodiment of theinvention.

FIG. 5 is a process diagram of a method of manufacturing an electroniccomponent package according to a third disclosed embodiment of theinvention.

FIG. 6 is a process diagram of a method of manufacturing an electroniccomponent package according to a fourth disclosed embodiment of theinvention.

FIG. 7 is cross-sectional view of an electronic component packageaccording to a fourth disclosed embodiment of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiments of the invention will be described below in more detail withreference to the accompanying drawings. In the description withreference to the accompanying drawings, those components are renderedthe same reference number that are the same or are in correspondence,regardless of the figure number, and redundant explanations are omitted.

FIG. 2 is a flowchart of a method of manufacturing an electroniccomponent package according to a first disclosed embodiment of theinvention, and FIG. 3 is a process diagram of a method of manufacturingan electronic component package according to a first disclosedembodiment of the invention. In FIG. 3 are illustrated an electroniccomponent package 30, a first carrier board 31 a, a second carrier board31 b, seed layers 32 a, 32 b, protrusion parts 33, an insulation layer34, holes 35, solder ball pads 36 a, a circuit pattern 36, bonding pads36 c, solder resist 37, an electronic component 38, chip pads 38 a, andmold material 39.

S21 of FIG. 2 is an operation of forming protrusion parts on a firstcarrier board, the corresponding process of which is shown in (a) ofFIG. 3. The operation of forming the protrusion parts 33 on the firstcarrier board 31 a can be divided into an operation of preparing a flatfirst carrier board 31 a, stacking a seed layer 32 a on the firstcarrier board 31 a by electroless plating, and forming the protrusionpart 33 on the surface of the seed layer 32 a in correspondence with thesolder ball pads 36 a. The protrusion parts 33 are formed by stacking adry film on the surface of the seed layer 32 a and then removing theremaining dry film besides the protrusion parts 33, through exposure anddevelopment processes. Meanwhile, the seed layer 32 a is formed so thatthe first carrier board 31 a may be detached readily. Therefore, if thefirst carrier board 31 a can be removed readily without an interposedseed layer 32 a, the process of stacking the seed layer 32 a isunnecessary.

S22 of FIG. 2 is an operation of stacking an insulation layer 34 on thefirst carrier board 31 a, and forming a circuit pattern 36, whichincludes bonding pads 36 c and solder ball pads 36 a, on the surface ofthe insulation layer 34, and the corresponding processes are shown in(b) to (e) of FIG. 3. As in (b) of FIG. 3, a second carrier board 31 b,on which the circuit pattern 36 including the bonding pads 36 c andsolder ball pads 36 a are formed, is aligned with the first carrierboard 31 a, which was formed previously in process (a) of FIG. 3, withan insulation layer 34 interposed in-between. The aligning is such thatthe protrusion parts 33 of the first carrier board 31 a and the circuitpattern 36 of the second carrier board 31 b face each other.

Meanwhile, the circuit pattern 36 illustrated in (b) of FIG. 3 ismanufactured on the surface of the second carrier board 31 b using asemi-additive method. Specifically, the seed layer 32 b and a dry filmare stacked in order on the surface of the second carrier board 31 b.Afterwards, exposure and development processes are performed to removeportions of the dry film where the circuit pattern 36 is to be formed.Then, plating the removed portions and removing the remaining dry filmresults in the circuit pattern 36 formed on the surface of the secondcarrier board 31 b, as illustrated in (b) of FIG. 3.

Drawing (c) of FIG. 3 shows the first carrier board 31 a and secondcarrier board 31 b stacked collectively, where the protrusion parts 33and the circuit pattern 36 including the solder ball pads 36 a andbonding pads 36 c are embedded inside the insulation layer 34.

Here, the protrusion parts 33 are stacked in positions that correspondwith the solder ball pads 36 a. Thus, it may be desirable that theprotrusion parts 33 be formed beforehand in process (a) at points thatcorrespond with the solder ball pad 36 a. Also, it may be desirable thatthe protrusion parts 33 be formed to have such a thickness that does notallow the insulation layer 34 to be interposed between the protrusionparts 33 and the solder ball pads 36 a. Meanwhile, the material used forthe insulation layer 34 is of a low hardness, so that the protrusionparts 33 may be embedded within. An example of such a material is pureresin.

Drawing (d) of FIG. 3 shows a process of removing the second carrierboard 31 b and the seed layer 32 b. The seed layer 32 b is removed byflash etching. Flash etching is an etching process performed with alower intensity than in regular etching, for removing the thin film ofseed layer. The result after the completion of this etching process iscomplete is as shown in (d) of FIG. 3. As in (d) of FIG. 3, the circuitpattern 36 including the solder ball pads 36 a and bonding pads 36 c isembedded in the insulation layer 34.

Drawing (e) of FIG. 3 shows a process of surface-treating the bondingpads 36 c, in which solder resist 37 is applied on the portions exceptfor the bonding pad 36 c portions. Afterwards, a Ni layer is stacked onthe bonding pads 36 c by electroless plating, and gold plating isperformed on the surface of the Ni layer by electroplating.

S23 of FIG. 2 is an operation of mounting an electronic component 38 onthe surface of the insulation layer 34 and electrically connecting theelectronic component 38 and the bonding pads 36 c. The bonding pads 36 care formed in positions that correspond with the chip pads 38 a of theelectronic component 38, and after positioning the chip pads 38 a on thesurfaces of the bonding pads 36 c, they are attached by flooring. Also,to protect the electronic component 38, a finishing is provided aroundthe electronic component 38 and insulation layer 34 using a moldmaterial 39.

S24 of FIG. 2 is an operation of removing the first carrier board 31 aand protrusion parts 33, the corresponding processes of which are shownin (g) and (h) of FIG. 3.

Drawing (g) of FIG. 3 shows a process of removing the first carrierboard 31 a and removing the seed layer 32 a. The first carrier board 31a is a sort of support, and is removed after the electronic component 38is mounted. After the first carrier board 31 a is removed, the seedlayer 32 a is removed. When the seed layer 32 a is removed, theprotrusion parts 33 are exposed. The exposed protrusion parts 33 areremoved by a wet treatment.

Drawing (h) of FIG. 3 shows the form of the electronic component package30 after the protrusion parts 33 are removed. Holes 35 are formed whenthe protrusion parts 33 are removed, and the solder ball pads 36 a areexposed to the exterior inside the holes 35. As portions of theinsulation layer 34 may remain on the solder ball pads 36 a, adesmearing process may further be performed to remove these.

FIG. 4 is a process diagram of a method of manufacturing an electroniccomponent package according to a second disclosed embodiment of theinvention. In FIG. 4 are illustrated an electronic component package 40,first carrier boards 41, seed layers 42 a, 42 b, protrusion parts 43,insulation layers 44, solder ball pads 46 a, circuit patterns 46,bonding pads 46 c, solder resist 47, electronic components 48, chip pads48 a, and mold material 49. In this embodiment, the efficiency isincreased in the manufacture of the electronic component packages 40, byperforming the procedures with two first carrier boards 41 attachedtogether.

Although this embodiment is generally the same as the first disclosedembodiment of FIG. 3, the memory packages 40 are manufactured withgreater efficiency by proceeding with the processes with two firstcarrier boards 41 a attached together. The following describes thisembodiment with reference to the process diagram of FIG. 4.

Drawing (a) of FIG. 4 shows the same process as (a) of FIG. 3, which isa process of forming the protrusion parts 43 on the first carrier board41 a.

In (b) of FIG. 4, two first carrier boards 41 a are attached facingopposite directions, such that the protrusion part 43 are exposed to theexterior, based on which the insulation layers 44 and the second carrierboards 41 b, having circuit patterns 46 that include the solder ballpads 46 a and bonding pads 46 c, are aligned in symmetry. Thus using thetwo first carrier boards 41 a attached together allows the processes tobe performed simultaneously.

Drawing (c) of FIG. 4 shows the insulation layers 44 and second carrierboards 41 b stacked symmetrically with respect to the two first carrierboards 41 a attached together. The protrusion parts 43 of the firstcarrier boards 41 a and the circuit patterns 46 of the second carrierboards 41 b are embedded in the insulation layers 44. It may bedesirable to use a material low in hardness for the insulation layers44, and in this embodiment, pure resin is used.

Drawing (d) of FIG. 4 shows a process of removing the second carrierboards 41 b and the seed layers 42 b. As the second carrier boards 41 band seed layers 42 b are removed, the circuit patterns 46 are uncoveredat the surfaces of the insulation layers 44.

Drawing (e) of FIG. 4 shows a process of applying solder resist 47 onportions excluding the bonding pads 46 c and afterwards surface-treatingthe bonding pads 46 c. The bonding pads 46 c are the portions that willlater be attached to the chip pads 38 a of the electronic components 38.

Drawing (f) of FIG. 4 shows a process of separating the two firstcarrier boards 41 a, and mounting an electronic component 38 on thebonding pads 46 c of each first carrier board 41 a. While the two firstcarrier boards 41 a are used attached together up until the process (e)of FIG. 4, the processes are performed with the first carrier boards 41a separated, starting from process (f) of FIG. 4. Drawing (f) of FIG. 4shows a process of attaching the chip pads 38 a and bonding pads 46 c tobe in correspondence and mounting the electronic components 38 on thesurfaces of the bonding pads 46 c. To protect the electronic component38, the mold material 49 is filled around the electronic component 38.Epoxy resin is used for the mold material 49.

Descriptions for (g) and (h) of FIG. 4 will be omitted, as they aresufficiently described for the first disclosed embodiment of FIG. 3.

FIG. 5 is a process diagram of a method of manufacturing an electroniccomponent package according to a third disclosed embodiment of theinvention. In FIG. 5 are illustrated an electronic component package 50,a first carrier board 51 a, a second carrier board 51 b, seed layers 52a, 52 b, protrusion parts 53, an insulation layer 54, solder ball pads56 a, a circuit pattern 56, bonding pads 56 c, resist 57, an electroniccomponent 58, chip pads 58 a, and mold material 59.

This embodiment shows a process of performing surface-treatment on thebonding pads 56 c, utilizing the seed layer 52 b as a lead wire. Theprocesses (a) to (c) of FIG. 5 are the same as the processes (a) to (c)of FIG. 3. Drawing (d) of FIG. 5 shows a process of removing the secondcarrier board 52 b. When the second carrier board 51 b is removed, theseed layer 52 b is uncovered.

Drawing (e) of FIG. 5 shows a process of removing the seed layer 52 b onthe surface of and around the bonding pads 56 c to which thesurface-treatment is to be applied and stacking resist 57 on the surfaceof the remaining seed layer 52 b. A dry film is used for the resist 57.Portions of the seed layer 52 b that are not removed act as a lead wirethat supplies an electrical current to the bonding pads 56 c. Thisprocess utilizes the seed layer 52 b as a lead wire, instead of forminga separate lead wire. The resist 57 prevents surface-treatment onportions other than the bonding pads 56 c.

Drawing (f) of FIG. 5 shows a process of mounting an electroniccomponent 58. In order to mount the electronic component 58, the seedlayer 52 b and resist 57 are removed in (e) of FIG. 5. Leaving the seedlayer 52 b may result in the circuit pattern 56 becoming electricallyconnected to undesired portions, and thus it may be advantageous toremove the seed layer 52 b. The process of mounting the electroniccomponent 58 after removing the seed layer 52 b is the same as that forFIG. 3, and thus detailed descriptions will not be provided on thismatter.

FIG. 6 is a process diagram of a method of manufacturing an electroniccomponent package according to a fourth disclosed embodiment of theinvention. In FIG. 6 are illustrated an electronic component package 60,first carrier boards 61 a, seed layers 62 a, copper foils 62 b,protrusion parts 63, copper clad laminates 64, solder ball pads 66 a,circuit patterns 66, bonding pads 66 c, solder resist 67, electroniccomponents 68, chip pads 68 a, and mold material 69.

This embodiment shows a process of stacking a copper clad laminate 64 onthe first carrier board 61 a, and afterwards removing the copper foil 62b to form the circuit pattern 66. Looking at this embodiment withreference to FIG. 6, (a) of FIG. 6 shows the same process as (a) of FIG.3, which is a process of forming protrusion parts 63 on the firstcarrier board 61 a.

Drawing (b) of FIG. 6 shows a process of attaching two first carrierboards 61 a such that the protrusion parts 63 face outward, and aligningthe copper clad laminates 64 in symmetry. In (c) of FIG. 6, the copperclad laminates 64 and first carrier boards 61 a are collectivelystacked. Here, the two first carrier boards 61 a are attached inconsideration of the fact that they will be separated in a subsequentprocess.

Drawing (d) of FIG. 6 shows a process of removing portions of the copperfoils 62 b to form the circuit patterns 66, including the solder ballpads 66 a and bonding pads 66 c. Drawing (e) of FIG. 6 shows a processof performing surface-treatment on the bonding pads 66 c, and drawing(f) shows a process of separating the two first carrier boards 61 a andafterwards mounting the electronic components 68. The followingprocesses are the processes of removing the first carrier boards 61 a,seed layers 62 a, and protrusion parts 63, as has been described for theembodiment of FIG. 3.

FIG. 7 is cross-sectional view of an electronic component packageaccording to a fourth disclosed embodiment of the invention. In FIG. 7are illustrated an electronic component package 70, an insulation layer74, solder ball pads 76 a, a circuit pattern 76, bonding pads 76 c,solder resist 77, an electronic component 78, chip pads 78 a, and moldmaterial 79.

In this embodiment, the bonding pads 76 c, which are to be electricallyconnected with the electronic component 78, are formed on one side of asingle layer of circuit pattern 76, and the solder ball pads 76 a, whichare to be connected with solder balls, are formed on the other side.These solder ball pads 76 a and bonding pads 76 c are portions of thecircuit pattern 76, and are concurrently formed when forming the circuitpattern 76.

The electronic component 78 has the form of a flip chip, with severalchip pads 78 a formed on the bottom surface. These chip pads 78 a areformed in positions that correspond with the bonding pads 76 c, and areelectrically connected to each other. Meanwhile, the electroniccomponent 78 is secured by means of the mold material 79. The solderball pads 76 a have surfaces exposed to the exterior, wheresurface-treatment is applied to the exposed portions. Thesurface-treatment is for enhancing the adhesion to the solder balls.

According the embodiments set forth above, the lengths of signal linesare shortened compared to the case of conventional electronic componentpackages, which allows quicker signal processing. Also, by means of thesemi-additive method, it is possible to form high-density circuits. Inaddition, since there is no wire bonding as in prior art, it is notnecessary to process holes, and as the circuit pattern is made of asingle layer, a superb heat-releasing effect is obtained.

While the present invention has been described with reference toparticular embodiments, it is to be appreciated that various changes andmodifications may be made by those skilled in the art without departingfrom the spirit and scope of the present invention, as defined by theappended claims and their equivalents.

1. An electronic component package comprising: an insulation layer; asingle layer of circuit pattern buried in the insulation layer andhaving a surface exposed at one side of the insulation layer, thecircuit pattern comprising a bonding pad and a solder ball pad; and anelectronic component mounted on one side of the insulation layer andelectrically connected with the bonding pad.
 2. The electronic componentpackage of claim 1, wherein a portion of the insulation layer is removedin correspondence with the position of the solder ball pad such that thesolder ball pad is exposed at the other side of the insulation layer.